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Abstract

A simulation apparatus and method for a logic circuit including a multi-port RAM effects simulation by provisionally representing input and output ports by use of a plurality of memory primitives and effecting the operation equivalent to the operation of the multi-port RAM. The address, data input and write enable terminals of input side memory primitives are supplied with write addresses, data inputs and write enable signals, respectively, and the chip select terminals thereof are supplied with '0' from a logic primitive. The write enable signals are also supplied to an AND logic primitive. The address terminals of output side memory primitives are supplied with respective read addresses, the data input terminals thereof are supplied with an output of the AND logic primitive, the chip select terminals thereof are supplied with '0' from a logic primitive, and the write enable terminals thereof are supplied with '1' from a logic primitive. Data outputs are derived from the respective output side memory primitives.

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First Claim