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Abstract

A Finite Impulse Response (FIR) digital signal processing circuit uses a double-accumulator technique to drastically reduce the number of multiply-accumulate operations which are necessary per sample of input data. The amount of reduction is dependent upon the shape of the filter function to be convolved. A double-accumulator (D-A) can be implemented by first providing a set of D-A coefficients, which are derived from the filter coefficient stream (FCS). Each D-A coefficient is multiplied by a separate input data sample. The products are summed together along with the result of a previous multiplication of the same D-A coefficients with different input data samples. This first sum is added to another number to form a second sum. The other number is the previous value of the second sum. The second sum is the result. The derived D-A coefficients are fewer and simpler than that required by the conventional FIR implementation. Since multipliers are complex, costly, bulky and limited in speed, the D-A method can lessen these constraints.

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