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Abstract

This invention relates to Single Instruction-stream Multiple Data-stream (SIMD) computer architecture. A SIMD computer typically comprises one or more single-chip Processing Element (PE) modules, each having one or more PEs and interfaces to multi-chip subsystems (MCSs). The PEs bear the brunt of a SIMD computation's workload, while MCSs provide coordination among PEs. In one aspect, this invention comprises augmenting the PE module with a multiplicity of clocks so as to regulate each PE and each MCS at its maximum rate of operation. In a further aspect, this invention comprises augmenting the PE modules with the ability to store instruction sequences and to provide repeated instruction sequences at the highest possible rate within the PE module. A SIMD computer allocates a greatest possible proportion of total chip-area to PEs. As determined by the electrical characteristics of the VLSI-based implementation process, the maximum operation rates of the PEs and MCSs exceed the rate of the global system clock. The invention comprises enhanced SIMD computers that exhibit the highest possible throughput-to-area ratio of any VLSI-based multi-processor.

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First Claim