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Abstract

An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory. When a match is found in said content addressable memory, the cell of data from the associated address in said random access is read out to its output destination port under control of said content addressable memory.

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First Claim