Integrated circuit I/O using a high performance bus interface
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United States of America Patent
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Apr 30, 1996
Issued Date -
N/A
app pub date -
Mar 31, 1994
filing date -
Apr 18, 1990
priority date (Note) -
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Importance
Abstract
A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.
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