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Abstract

A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

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First Claim