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Abstract

In a cache memory test method for an information processing apparatus, data for testing cache memories is set in a main memory such that data values of the data have regularity. The data is loaded from the main memory into each of the cache memories. The data is equal or larger in amount than the capacity of each of the cache memories. Information indicating a cache hit indicating that the data is read out from one of the cache memories when the main memory is accessed to read out the data therefrom, or information indicating a cache mishit indicating that the data is not read out from any one of the cache memories is recorded to form a cache hit/mishit information table. Whether each of the cache memories is in a normal/abnormal condition is determined from the state of occurrence of cache hits and cache mishits indicated by the cache hit/mishit information table. Whether each of the cache memories is in a normal/abnormal condition is determined by checking, on the basis of the regularity, correctness of a data value with respect data for which a cache hit is determined in the third step. The capacity of each of the cache memories is determined on the basis of the amount of data for which cache hits are determined.

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