Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations
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United States of America Patent
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Apr 30, 1996
Issued Date -
N/A
app pub date -
Jan 24, 1995
filing date -
Jan 7, 1992
priority date (Note) -
Expired
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Abstract
Two new classes of interconnection networks are described. The new classes of interconnection networks are referred to herein as the hierarchical shuffle-exchange (HSE) and hierarchical de Bruijn (HdB) networks. The new HSE and HdB networks are highly regular and scalable and are thus well suited to VSLI implementation. In addition, they can be adjusted to match any set of packaging constraints. These new networks are also efficient in supporting the execution of a wide range of algorithms on computers whose processors are interconnected via one of the networks fabricated in accordance with the teachings of the invention. Such computers, also contemplated by the invention, are referred to herein as HSE and HbB computers. Furthermore, methods for implementing the aforementioned wide range of algorithms, particularly those in the classes of Ascend and Descend algorithms, on the novel HSE and HdB computers, constitute a further aspect of the invention.
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