Six transistor dynamic content addressable memory circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5515310
SERIAL NO

08357848

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Abstract

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A content addressable memory cell includes six transistors connected together to perform memory read, memory write, and matching operations. This cell has the ability to perform typical memory write and memory read operations as well as the capability of signalling whether or not its stored data matches data that is being searched for. A cross-coupling scheme is used in the memory cell so that a high potential will always be stored on the gate of a transistor whose source is at ground. This cross-coupling scheme increases the amount of charge stored on the storage transistor and decreases the required frequency of refresh operations. In addition to the transistors configured to store data, an additional transistor configured as a diode is used as a rapid discharge path to maximize the efficiency of the cell during a read operation. During a match operation another transistor is utilized to discharge the Match line quickly in the event the stored data does not match the data that is being searched for.

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Patent Owner(s)

Patent OwnerAddress
COMTECH TELECOMMUNICATIONS CORP105 BAYLIS ROAD MELVILLE NY 11747

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Winters, Kel D Moscow, ID 7 414

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