Variable-size first in first out memory with data manipulation capabilities
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 7, 1996
Grant Date -
N/A
app pub date -
Nov 4, 1994
filing date -
Nov 4, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully