Circuit and method for reducing delays associated with contention interference between code fetches and operand accesses of a microprocessor
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United States of America Patent
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May 7, 1996
Grant Date -
N/A
app pub date -
Feb 8, 1994
filing date -
Feb 8, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
An access control unit for a microprocessor receives fetch requests and operand access requests from a CPU of the microprocessor, and issues the requests to a bus/cache unit in a manner which reduces interference between fetch requests and operand access requests. Fetch addresses for fetch requests that cannot be immediately performed by the bus/cache unit are placed in a fetch address queue, allowing such fetch requests to be postponed. Operand access requests received by the access control unit are performed prior to postponed fetch requests. Thus, the execution unit of the CPU can continue to execute instructions which require operand accesses without waiting for pending fetch requests to be performed. Fetch requests that have been postponed by the access control unit are attempted on every clock cycle for which no operand access request is pending.
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