Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
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United States of America Patent
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May 14, 1996
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N/A
app pub date -
Jun 3, 1994
filing date -
Jun 3, 1994
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Abstract
A method is provided for forming a planarization structure of dielectrical materials upon a substrate topography. The dielectric materials are deposited as first and second insulating layers. The second, and then the first insulating layers are partially removed by chemical-mechanical polish (CMP). Prior to CMP, the second insulating layer of variable chemical and mechanical properties can be fixed at a preferred chemical or mechanical characteristic which makes it more or less susceptible to subsequent CMP. Accordingly, the present invention utilizes a second insulating layer of adjustable properties necessary to more adequately planarize during application of CMP.
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