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Abstract

A state machine synthesis tool, a state table script generator, a state table extraction tool, a simulation driver, a simulator, and an interactive reporter, are provided to verify the design and implementation of finite state machines (FSMs). The synthesis tool takes a formal specification of a logic circuit where FSMs are embedded as input, and generates a gate level specification of the logic circuit. The state table script generator takes the same formal specification of the logic circuit as input, and generates state table extraction command files for the FSMs. The state table extraction tool takes the gate level specification of the logic circuit and the state table extraction command files of the FSMs as inputs, and generates state tables for the FSMs. The simulation driver takes the state tables of the FSMs as inputs, and in cooperation with the simulator, which takes the gate level specification of the logic circuit and a number of functional vectors as inputs, simulates the logic circuit and generates simulation results of the FSMs. Finally, the interactive reporter takes the simulation results of the FSMs, the state tables and user commands as inputs, and generates the analysis results that allow verification of the design and implementation of the FSMs.

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First Claim