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Abstract

A mechanism and procedure for providing an efficient pipeline for reading and writing information to a multiple ported segment register file (SRF) in different pipestages. The present invention is operable, in one embodiment, within an address generation unit (AGU) of a processor and is implemented to write the SRF during a particular clock phase of a pipestage and to read to the SRF during another clock phase of another pipestage of the AGU pipeline of a pipelined processor. The read and write of different pipestages associated with separate instructions may occur within a same clock cycle. The write occurs before the read. By reading and writing to the AGU in alternate clock phases, the read and write operations of the SRF do not conflict even though they span different pipestages of the pipeline. Therefore, pipestages of the present invention are not in resource conflict over the SRF read and write operations which occur in a same clock cycle. Specifically, within the scope of the present invention, the SRF may be read during the low phase of a clock cycle while the SRF may be written during the high phase of a clock cycle for different instructions. Alternatively, the above phase relationships may be inverted.

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First Claim