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Abstract

A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component. Then an optimizer determines which datapath expressions can be 'combined', or performed by a single library element, so as to reduce the circuit layout area used. The optimizer can combine multiple datapath expressions so as to use datapath circuit elements having multiple parallel outputs. Finally, one library element is selected for each datapath expression, or combined expression, on the basis of circuit area, speed, power or other optimization criteria. Then the connections between the selected circuit components are computed and the resulting circuit is output in the form of a circuit netlist.

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