Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 21, 1996
Issued Date -
N/A
app pub date -
May 1, 1995
filing date -
Jul 19, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A logic and routing cell for constructing a programmable gate array. The gate array may be constructed by tiling a wafer surface with this single logic and routing cell design. The logic and routing cell includes both the logic cell and the routing circuitry needed to connect that logic cell to all levels of a hierarchical routing system for making connections between the various logic cells.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully