Process for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure

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United States of America Patent

PATENT NO 5521108
SERIAL NO

08121679

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Abstract

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A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

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Patent Owner(s)

Patent OwnerAddress
LSI LOGIC CORPORATION1551 MCCARTHY BOULEVARD MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kapoor, Ashok Palo Alto, CA 18 493
Rostoker, Michael D Boulder Creek, CA 204 14387

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