Semiconductor test system including a novel driver/load circuit
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United States of America Patent
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-
May 28, 1996
Grant Date -
N/A
app pub date -
Nov 21, 1994
filing date -
Nov 21, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A novel pin electronics design and method is taught which serves to minimize the capacitive loading of the driver and load portion of the pin electronics. The driver and load circuitry are combined to form a novel driver/load circuit, thereby reducing capacitive loading, simplifying circuit structure, and improving the speed of operation of the test system and the accuracy of the test.
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