Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation

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United States of America Patent

PATENT NO 5521529
SERIAL NO

08459960

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Abstract

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A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

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Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION5555 NE MOORE CT HILLSBORO OR 97124

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Agrawal, Om P Los Altos, CA 127 5023
Moyer, Bryon I Cupertino, CA 2 121
Schmitz, Nicholas A Sunnyvale, CA 12 879
Sharpe-Geisler, Bradley A San Jose, CA 97 2796

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