Importance

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Abstract

A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing predetermined functions, and a decode state decoding the fetched instructions to issue parallel-processable instructions to related functional units. The decode stage includes a decoder determining whether a branch instruction is included in the received instructions and whether a branch is generated according to the branch instruction. The decoder links a write delaying flag indicating whether the instruction is after a branch instruction and a validity flag indicating whether the instruction is valid to the instruction on issuing the instruction to a functional unit. The functional unit includes an execution stage executing an instruction and a write back stage changing a machine state according to the result of execution in the execution stage. The superscalar-type processor comprises a control circuit forbidding changing of the machine state by a write back stage when a branch is generated according to the branch instruction. The control circuit sets the write back stage in a state of delaying changing of the machine state when it is not yet determined whether a branch is generated according to the branch instruction and executes changing of the machine state with the write back stage when it is determined that no branch is generated according to the branch instruction.

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First Claim