Analog-to-digital converter with offset reduction loop
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United States of America Patent
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Jun 4, 1996
Grant Date -
N/A
app pub date -
Jan 18, 1994
filing date -
Jan 18, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An analog-to-digital converter with an offset reduction loop detects the presence/absence of an analog input signal having a zero mean value. The analog input signal is converted to a digital signal by the analog-to-digital converter. The least significant bits of the digital signal are compared with a decision threshold to generate an indicator signal representing the presence/absence of the analog input signal. Arbitrary d.c. offsets in the digital signal are compensated by generating a d.c. offset compensation signal from the most significant bit of the digital signal with respect to a mid-logic reference voltage. The d.c. offset compensation signal is added to the analog input signal prior to conversion to the digital signal.
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