Non-volatile memory cell for programmable logic device
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United States of America Patent
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Jun 4, 1996
Grant Date -
N/A
app pub date -
Mar 16, 1995
filing date -
Mar 16, 1995
priority date (Note) -
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Abstract
The present invention provides a memory cell which includes a pair of flash EEPROM cells. One flash EEPROM cell is programmed and the other flash EEPROM cell is simultaneously erased by a single programming pulse. Because the configuration memory cell includes flash EEPROM cells, and therefore is non-volatile, a power down does not require reprogramming or refreshing of the configuration bit stored in the memory cell.
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