Method and apparatus for verifying the programming of multi-level flash EEPROM memory
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United States of America Patent
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Jun 4, 1996
Grant Date -
N/A
app pub date -
Jun 2, 1994
filing date -
Jun 2, 1994
priority date (Note) -
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Abstract
A programming verify circuit for controlling the memory cells to which programming voltages are applied, the circuit including a comparator for testing the state of each cell being programmed with the state to which the cell is being programmed, and a program load circuit which responds to the result of the test by the comparator to hold a condition for each memory cell being programmed to indicate whether the memory cell should be further programmed, each program load circuit including circuitry for precluding the holding of a condition indicating further programming is necessary once the associated memory cell has been initially verified as programmed by the comparator.
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