Semiconductor memory device with a substrate bias voltage generation circuit as a power supply of a word line driver circuit
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United States of America Patent
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Jun 4, 1996
Grant Date -
N/A
app pub date -
Feb 15, 1995
filing date -
Feb 16, 1994
priority date (Note) -
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Abstract
In a CMOS type static RAM, a substrate bias voltage VPP higher than a power supply voltage supplied from an outer unit is supplied to an N type substrate region of a PMOS transistor of a CMOS inverter forming a word line driving circuit to bias the N type substrate region to the bias voltage VPP and to a power supply terminal of the CMOS inverter as a power supply voltage. Whereby, resistance of storage data to incidence of radioactive rays is increased just after writing to a storage node of a memory cell is ended, and a soft error generation rate can be easily reduced.
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