System and method for controlling the competition between processors, in an at-compatible multiprocessor array, to initialize a test sequence
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United States of America Patent
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Jun 4, 1996
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N/A
app pub date -
Feb 27, 1995
filing date -
Feb 27, 1995
priority date (Note) -
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Abstract
A multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, and wherein a 'semaphore port' SP is coupled to all processors, this port SP being adapted to normally signal 'GO', but after 'first-access' by a said processor, which thus becomes a 'selected processor', to thereupon signal 'STOP' to all other, 'non-selected', processors, and so deny access until a given test sequence is completed.
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