Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers
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United States of America Patent
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Jun 4, 1996
Issued Date -
N/A
app pub date -
Dec 23, 1994
filing date -
Aug 23, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.
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