Method and apparatus for partial and full stall handling in allocation

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5524263
SERIAL NO

08201560

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated. The present invention, upon detection of a partial stall, allocates a partial number of instructions within the clock cycle that causes the partial stall and updates a retirement entry pointer to the ROB but does not advance the resource pointers. Upon the clock cycle of the deassertion of the partial stall, the remainder of the instructions are allocated to the resource buffers and the resource pointers are advanced. In the event a full and partial stall are asserted concurrently, the full stall takes priority.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Griffth, James S Aloha, OR 1 68
Gupta, Shantanu R Beaverton, OR 9 424
Hegde, Narayan Beaverton, OR 5 155

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