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Abstract

This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall. The buffer circuitry preferably is used for buffering processor requested data transfers. Also a further cache buffer having a plurality of registers is used in buffering instruction cache service requests. The data transfer controller includes refresh registers coupled to the external sequencer. This provides data refreshing of dynamic random access memories. The data transfer controller further includes request prioritization circuitry coupled to the pipeline controller for prioritization of data transfer requests to the pipeline controller.

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First Claim