Importance

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Abstract

A system buffers first and second data buses having asynchronous, different frequency clocks. The system comprises a data buffer interposed between the first and second data buses to receive data from the first bus and supply data to the second bus. The also comprises a write address generator, coupled to the first bus to receive a data available signal and coupled to the data buffer, for generating an address in the data buffer to store the data received from the first bus. The data available signal increments the write address generator. A load record register is coupled to receive an indication that data is being written from the first data bus into the data buffer, and tracks locations in the data buffer which have received data from the first data bus. A read address generator is coupled to the data buffer, and generates an address of the next data, if any, that is stored in the data buffer to be read onto the second data bus. A conversion and comparison circuit is coupled between the read address generator and the load record, and determines if the address in the data buffer generated by the read address generator contains data to be read onto the second data bus, and if so, enables transmission of the data at the address to the second data bus and enables incrementing of the read address generator when or after said data is read to the second data bus.

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First Claim