ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof

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United States of America Patent

PATENT NO 5526277
SERIAL NO

08355105

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Abstract

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A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

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Patent Owner(s)

Patent OwnerAddress
LSI LOGIC CORPORATIONSANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bootehsaz, Ahsan Santa Clara, CA 4 238
Dangelo, Carlos San Jose, CA 43 3950
Nagasamy, Vijay K Mountain View, CA 2 146
Rajan, Sreeranga P Sunnyvale, CA 47 2427

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