Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations
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United States of America Patent
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Jun 11, 1996
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app pub date -
Jun 20, 1995
filing date -
Dec 30, 1993
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Abstract
A method and system, in which the relative physical placement of configurable logic blocks, signal routing networks, and clock distribution trees of the FPGA implementation is preserved on the mask programmable logic cell (MPLC) substrate after the conversion process is completed. By constraining the physical placement of corresponding structures on the MPLC substrate at the network level of the MPLC implementation, the relative signal and clock delays presented during the FPGA implementation are substantially maintained in the MPLC implementation, thereby assuring functional equivalence between the FPGA and MPLC implementations.
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