High speed global row redundancy system
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United States of America Patent
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Jun 18, 1996
Grant Date -
N/A
app pub date -
Sep 29, 1994
filing date -
Sep 29, 1994
priority date (Note) -
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Abstract
A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.
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