Programmable multi-level bus arbitration apparatus in a data processing system

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United States of America Patent

PATENT NO 5528767
SERIAL NO

08407236

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Abstract

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A programmable multi-level bus arbitration apparatus for computer systems which implements dynamic arbitration for the grant of control over a system bus by one of a number of bus master devices. A number of programmable restricters each receive a system bus request signal issued by a corresponding one of the bus master devices competing for the control over the system bus. The restricters block or relay the bus request signal. A programmable priority arbiter receives an output of each of the restricters for arbitration to grant control of the system bus to a selected one of the bus master devices based on a pre-programmed priority scheme. A communication protocol handler receives and monitors the status of the bus enable signal for generating a bus busy signal to control the issuing of a verified bus request signal by one of the restricters or the blocking of the bus request signal based on the status of the bus busy signal.

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Patent Owner(s)

Patent OwnerAddress
UNITED MICROELECTRONICS CORPHSIN-CHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chang-San Taipei, TW 12 82

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