Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes
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United States of America Patent
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Jun 25, 1996
Grant Date -
N/A
app pub date -
May 16, 1994
filing date -
May 16, 1994
priority date (Note) -
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Abstract
A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the 'suspended' normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.
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