Data packet switching system having DMA controller, service arbiter, buffer type managers, and buffer managers for managing data transfer to provide less processor intervention
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United States of America Patent
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Jun 25, 1996
Grant Date -
N/A
app pub date -
Jun 14, 1993
filing date -
Jun 14, 1993
priority date (Note) -
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Abstract
A multi-purpose direct memory access packet control system for moving packets within a multi-processor computer system. The data memory is allocated into a number of unique data spaces suitable for storage of packets. Each data space is controlled by a unique type of buffer manager. Different buffer formats such as circular, linear, and offset are provided without the intervention of the processor and its associate software. Data packets are rapidly transmitted from an input buffer to the appropriate section of the memory and vice versa.
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