Methods and apparatus for test and burn-in of integrated circuit devices
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United States of America Patent
Stats
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Jul 2, 1996
Grant Date -
N/A
app pub date -
Jul 19, 1994
filing date -
Jul 19, 1994
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Methods and specially adapted reusable test carriers provide for burn-in test of semiconductor integrated circuit devices and economical production of known good dice (KGD). Methods for temporary flip-chip mounting of IC wafers or dice use a hierarchy of solder melting points in combination with improved reusable carrier substrates. IC chip wafers having high-melting-temperature flip-chip terminals are coated with a predetermined volume of a sacrificial solder having a significantly lower melting temperature. A reusable temporary carrier is provided, in a range of sizes adapted for a wafer, small numbers of IC dice, or an individual die, For full-wafer burn-in, the reusable carrier has edge connector terminals. For testing individual dice or a small number of dice, the reusable carrier has conductive elements in a pattern matching each IC dies terminal pattern. The same or opposite side of the reusable carrier has pins or ball-grid array matching a conventional burn-in socket. A preferred reusable carrier consists of separable parts: a substrate customized to carry specific dice for burn-in, and a 'universal' carrier package adapted to fit standard test sockets. After burn-in testing, the known good dice are removed by a low-temperature reflow, and attached to permanent substrates by conventional high-temperature reflow. The test carriers are re-usable after cleaning. A carrier structure similar to the preferred separable structure is specially adapted for testing and/or permanent packaging of IC chips which utilize wire-bond connections.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| LIANG LOUIS H | Not Provided |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Liang, Louis H | 10601 Creston Dr., Los Altos, CA 94024-7420 | 27 | 1759 |
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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