Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
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United States of America Patent
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Jul 2, 1996
Issued Date -
N/A
app pub date -
Apr 3, 1995
filing date -
Jul 17, 1992
priority date (Note) -
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Abstract
A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of more than two areas into which functions (active elements, or circuits) are assigned according to their area requirements. The die is iteratively sub-partitioned.
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