Fault-tolerant processing system

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United States of America Patent

PATENT NO 5533188
SERIAL NO

07963170

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Abstract

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A fault-tolerant, fiber optic interconnect, or backplane, which serves as a via for data transfer between modules. Fault tolerance algorithms are embedded in the backplane by dividing the backplane into a read bus and a write bus and placing a redundancy management unit (RMU) between the read bus and the write bus so that all data transmitted by the write bus is subjected to the fault tolerance algorithms before the data is passed for distribution to the read bus. The RMU provides both backplane control and fault tolerance.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL AERONAUTICS AND SPACE ADMINISTRATION THE (NASA)WASHINGTON DC 20546

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Palumbo, Daniel L Newport News, VA 6 65

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