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Abstract

A board-mounted memory array includes a plurality of memory modules, each module N bits wide by M bits long, the memory array including YM addresses of words that are XN bits long, where X and Y are integers. Each word is comprised of N bits from a common address value in each of X modules. The memory array includes memory interface logic mounted on the board which accesses the memory array in response to address signals. The memory interface logic is configured to use a first address procedure to access individually addressed words in the memory array at a first rate and, upon command, to use a second address procedure to sequentially access a span of contiguous addresses at a second, higher rate. A controller is coupled to the memory interface logic and enables application of address signals generated external to the board. Hardware test circuitry is resident on the board and controls the memory interface logic to implement the second address procedure and to apply test signals to a plurality of contiguous addresses in the memory array in accordance with a test protocol and to analyze output signals fed to the memory interface logic from the addressed memory words. The hardware test circuitry implements a protocol which causes application to the plurality of contiguous addresses of plural N bit test groups, each address receiving identical N-bit test groups across all bit positions in an addressed word.

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