CMOS power-on reset circuit using hysteresis
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United States of America Patent
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Jul 9, 1996
Grant Date -
N/A
app pub date -
Feb 13, 1995
filing date -
Feb 13, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply includes a voltage clamping stage (14) and a hysteresis switching stage (16). The voltage clamping stage (14) is formed of an N-channel resistor (M1), a first resistor (R1), and a second resistor (R2). The hysteresis switching stage (16) includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).
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