Shared buffer switching module
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United States of America Patent
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Jul 9, 1996
Grant Date -
N/A
app pub date -
May 25, 1994
filing date -
Sep 26, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
This invention relates to a switch module for use in an asynchronous transfer mode (ATM) system incorporating a shared buffer memory where incoming data cells are stored and subsequently transferred to exit ports. An incoming data cell is stored at a vacant buffer memory address on an interleaved, word-by-word basis and the address is placed in an appropriate priority queue in the appropriate exit port for the data cell. When time is available for transmission from the exit port, the data cell corresponding to the address at the head of the highest priority queue is sent to the exit port and transmitted.
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