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Abstract

A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.

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First Claim