Shared memory for split-panel LCD display systems
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United States of America Patent
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Jul 16, 1996
Grant Date -
N/A
app pub date -
Aug 4, 1993
filing date -
Aug 4, 1993
priority date (Note) -
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Abstract
The video memory and the half-frame buffer frame accelerator of a dual scan LCD display are integral in a single memory device. Flat-panel read and write cycles to the frame accelerator designed area inside the memory are optimized in order to minimize memory bandwidth requirements. Extra memory space in the memory device may be used to buffer multiple half-frames of shaded data in such a manner as to save a considerable amount of power in the LCD display graphics system.
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