Low pin count-wide memory devices and systems and methods using the same
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United States of America Patent
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Jul 16, 1996
Grant Date -
N/A
app pub date -
Aug 31, 1995
filing date -
Aug 31, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and multiplexed input/output during a second time period.
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