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Abstract

A cache memory controller and method for dumping the contents of a cache directory and a cache data random access memory (RAM) are described. In order to dump the contents of the cache directory, access to the cache data RAM is disabled by disabling the cache controller. Then, address tags within the cache directory are read sequentially from a reserved register. In order to dump the contents of the cache data RAM, new addresses are allocated to data in the cache data RAM. This is done, for example, by blocking writes to the cache data RAM while enabling read access from the cache data RAM and both read and write access to the cache directory. A reserved block of cacheable memory within, for example, the main system memory, is accessed. When the reserved block of cacheable memory is accessed, address tags for addresses of the reserved block of cacheable memory are written into the cache directory; however, data from the reserved block of cacheable memory is not written into the cache data RAM. Data in the cache data RAM is now accessible using addresses for the reserved block of cacheable memory. In a preferred embodiment, the cache controller includes non-cacheable RAM registers, multiplexers, a sequencer, a cache data RAM controller having logic circuitry for suppressing/gating cache write enable signals, a system controller interface, configuration/diagnostic registers and a cache directory set.

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