Process for fabricating MOS transistors having full-overlap lightly-doped drain structure

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United States of America Patent

PATENT NO 5538913
SERIAL NO

08558958

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Abstract

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A process for fabricating a MOS transistor having a full-overlap lightly-doped drain is disclosed. The MOS transistor is fabricated on a semiconductor silicon substrate that has formed thereon a field oxide layer that defines the active region of the MOS transistor. A field oxide layer is first used as the shielding mask for implanting impurities into the active region thereby forming a lightly-doped region. A shielding layer is then formed with an opening over the surface of the substrate. The opening has two sidewalls that generally define the channel region for the MOS transistor. A gate insulation layer is then formed over the surface of the substrate within the confinement of the opening. Conducting sidewall spacers are then formed over the sidewalls of the opening. The shielding layer and conducting sidewall spacers are then utilized as the shielding mask for implanting impurities into the lightly-doped region, thereby forming the channel region for the MOS transistor. A conducting layer is then formed over the surface of the gate insulation layer in the space as confined within the conducting sidewall spacers, wherein the conducting layer and the conducting sidewall spacers constitute the gate for the MOS transistor. The shielding layer is then removed. The gate and field oxide layer are used as the shielding mask for implanting impurities into the substrate, thereby forming a heavily-doped region, wherein the lightly-doped region completely overlaps the gate, and extends into the drain and source regions of the MOS transistor.

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Patent Owner(s)

Patent OwnerAddress
UNITED MICROELECTRONICS CORPORATIONNO 3 LI-HSIN RD II SCIENCE-BASED INDUSTRIAL PARK HSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hong, Gary Hsinchu, TW 225 4351

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