Method and apparatus for analyzing finite state machines
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United States of America Patent
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Jul 23, 1996
Grant Date -
N/A
app pub date -
Aug 3, 1994
filing date -
Aug 3, 1994
priority date (Note) -
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Abstract
A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM). This embodiment requires at least one test vector. The computer system comprises a memory and a processor. The memory is for storing the hardware description and the test vector. The processor, coupled to the memory, uses the hardware description and generates state information corresponding to the FSM. The processor, using the state information, further generates a first description. The first description includes a description for monitoring states and signals in the hardware description. The processor, using the test vector, the hardware description and the first description, further generates the test coverage summary.
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