Redundancy circuit device

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United States of America Patent

PATENT NO 5539698
SERIAL NO

08378268

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Abstract

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The redundancy circuit device includes a main word line 1 for selecting a first memory area and a subsidiary word line 2, and a spare subsidiary word line 4 for selecting a second memory area (in which spare memory cells are arranged). In case a defective memory cell exists in the first memory cell area, the address is programmed by a redundancy program circuit 14 of a redundancy circuit 41 (provided for each section) of a section decoder 42. Further, when a row partial signal outputted from a row partial decoder 13 hits a defective memory cell, the spare subsidiary word line 4 is selected through the redundancy program circuit 14 to select the spare memory cell, without selecting the subsidiary word line 2. In a memory device of double word line system, a defective memory cell can be replaced with a spare memory cell in unit of each of a plurality of the subsidiary word lines connected to the main word line, thus improving the redundancy efficiency and thereby increasing the production yield of the memory chip.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA72 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI KANAGAWA-KEN JAPAN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Suzuki, Azuma Toyko-to, JP 14 224

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