Method and apparatus for forming an integrated circuit including a memory structure

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5541850
SERIAL NO

08245207

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A set of circuit specifications including an internal memory structure is developed and then described in a hardware description language that is entered into a computer system. The circuit description is then synthesized on the computer to form a netlist to specify the circuit. From this netlist, an integrated circuit is produced on a semiconductor die, which is then packaged for use. A method for synthesizing a netlist from a hardware description including an internal memory structure includes converting the hardware description into an internal signal list, which contains an indication of the presence of an internal memory structure in the described circuit. For each memory structure indicated, synthesis is performed using a memory cell library, and compatibility between the hardware description for the circuit and the internal memory structure specified is determined. When compatibility is found, the internal memory structure is instantiated into the netlist for the circuit. A central processing unit (CPU) is connected to a keyboard used to input a hardware description of a circuit. Further included is a hardware description processor implemented on the CPU that creates mask generation data for use with a mask generator to form an integrated circuit. An internal memory structure as described in the hardware description of the circuit is thereby included in the circuit.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
VLSI TECHNOLOGY INC1109 MCKAY DRIVE SAN JOSE CA 95131

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mahmood, Mossaddeq San Jose, CA 7 819
Vander, Zanden Nels B Mountain View, CA 1 35

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation