Method for manufacturing offset polysilicon thin-film transistor
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United States of America Patent
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Aug 6, 1996
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N/A
app pub date -
Dec 27, 1994
filing date -
Dec 28, 1993
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Abstract
In a method for fabricating an offset polysilicon thin-film transistor through the formation of silicide, the width of offset regions can be controlled as a narrow width of below 1 .mu.m. Drain voltage is decreased due to the reduction of the offset regions' width. The effect of an increased parallel resistance and a bias voltage dependency of an overlap capacitance due to the arrangement of low concentration ion region reduces leakage current and improves the response to applied voltages. Also, gate voltage is decreased due to the decreased gate resistance when the polysilicon of the gate is substituted with the silicide.
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